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An effective on-chip preloading scheme to reduce data access penalty

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2 Author(s)
Baer, Jean-Loup ; Dept. of Comput. Sci. & Eng., Univ. of Washington, Seattle, WA, USA ; Tien-Fu Chen

Conventional cache prefetching approaches can be either hardware-based, generally by using a one-block-lookahead technique, or compiler-directed, with insertions of non-blocking prefetch instructions. We introduce a new hardware scheme based on the prediction of the execution of the instruction stream and associated operand references. It consists of a reference prediction table and a look-ahead program counter and its associated logic. With this scheme, data with regular access patterns is preloaded, independently of the stride size, and preloading of data with irregular access patterns is prevented. We evaluate our design through trace driven simulation by comparing it with a pure data cache approach under three different memory access models. Our experiments show that this scheme is very effective for reducing the data access penalty for scientific programs and that is has moderate success for other applications.

Published in:

Supercomputing, 1991. Supercomputing '91. Proceedings of the 1991 ACM/IEEE Conference on

Date of Conference:

18-22 Nov. 1991