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A 1 MHz Bandwidth, 6 GHz 0.18 \mu m CMOS Type-I \Delta \Sigma Fractional-N Synthesizer for WiMAX Applications

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3 Author(s)
Hedayati, H. ; Marvell Semicond., Inc., Santa Clara, CA, USA ; Khalil, W. ; Bakkaloglu, B.

A 6 GHz Type-I fractional-N PLL with noise-cancelling DAC and discrete-time sample and hold loop-filter is presented. The 1 MHz bandwidth PLL utilizes an inherently linear PFD and noise-cancelling charge-pump DAC circuit to reduce quantization noise by more than 25 dB. The worst case near-integer in-band spur is measured at -61 dBc and the integrated RMS phase error is - 42 dBc. The measured in-band phase noise at 300 kHz offset from the 6.12 GHz carrier is -102 dBc/Hz and out-of-band phase noise at 3 MHz offset is -130 dBc/Hz. The PLL loop settling time for an accuracy of 0.01 ppm and a frequency step of 60 MHz is less than 11 ¿ s. The synthesizer is fabricated in a 0.18 ¿m CMOS technology with 6 metal layers and consumes 26 mA from a 1.8 V power supply.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:44 ,  Issue: 12 )

Date of Publication:

Dec. 2009

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