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A combined finite difference and analytic expression approach to crossover capacitance in a multilayer dielectric environment

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3 Author(s)
Guang-Wen Pan ; Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA ; M. Toupikov ; B. K. Gilbert

The capacitances in the crossover regions of orthogonal transmission lines of finite thickness, fabricated on structures of the approximate dimensions of an integrated circuit, are evaluated in this paper by means of a combined finite difference and analytic expression method. The three-dimensional (3-D) finite difference method (FDM), using very fine mesh grids, is applied to an artificially defined region only a few microns in thickness, where orthogonal transmission lines on different metal layers of an integrated circuit cross one another. In the 600-μm thick dielectric region above the ground plane on the lower surface of an integrated circuit, analytic expressions of the solution to the Laplace equation are formulated. An artificial boundary is assumed to separate the substrate of the 600-μm thick integrated circuit from the thin active region on its uppermost surface where the active circuits and interconnects are actually fabricated, creating two separate regions which are treated using different approaches. An iterative procedure is employed to create a continuous interface between solutions across the boundary of the two regions generated by the two methods. The algorithm converges rapidly to very accurate solutions. The errors between this simulation method and laboratory measurements are within 8% for very small absolute values in the femtoFarad (fF) range. The field solutions are then converted into the equivalent circuit parameters. Finally, the waveshapes of propagating signal pulses are simulated by a networking program in a general electromagnetic modeling tool suite referred to as the Mayo Graphical Integrated Computer Aided Design Suite, or MagiCAD, in which the equivalent circuit model and capacitance values of the crossover problem are integrated

Published in:

IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B  (Volume:19 ,  Issue: 3 )