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Partial Bitstream 2-D Core Relocation for Reconfigurable Architectures

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3 Author(s)
Rossmeissl, C. ; Dept. of Electr. & Comput. Eng., Univ. of Arizona, Tucson, AZ, USA ; Sreeramareddy, A. ; Akoglu, A.

Field programmable gate arrays (FPGAs) potentially offer enhanced reliability, recovery from failures through partial and dynamic reconfigurations, and eliminate the need for redundant hardware typically used in fault-tolerant systems. Our earlier work on scalable self-configurable architectures for reusable space systems (SCARS) describes a partial reconfiguration based self-healing architecture. The implementation of this architecture with the currently available industry tools has taught us a few valuable lessons. Generating the partially reconfigurable cores has acute restrictions that limit our ability to relocate the cores to other regions of the FPGA leading to poor area utilization. State of the art relocation approaches in the academia employ complex relocation management mechanisms which prohibit these solutions to operate at run time. In this paper, we propose a methodology for run-time 2-D core relocation to overcome the above issues. We show that our approach increases reconfiguration area utilization by 36% and reduces partial bitstream storage memory usage by 91% when compared to our base implementation. Conventional solutions restrict a given functionality to be partially reconfigured in a predetermined area. This technology enables the designer to move any core to anywhere on the FPGA fabric providing more resource availability when recovering from failure.

Published in:

Adaptive Hardware and Systems, 2009. AHS 2009. NASA/ESA Conference on

Date of Conference:

July 29 2009-Aug. 1 2009