Deep submicron: is test up to the challenge?

ICs fabricated in increasingly deep submicron technologies are fundamentally shifting the problem areas on which to focus when testing these devices. Several major paradigm shifts are required in order for current test technologies to be extended to meet the challenges. In the past, chip sizes and operational speeds were such that numerous assumptions could be employed throughout the manufacturing test process which greatly eased pattern generation and application. Among those assumptions were: high stuck-at fault coverage is sufficient to guarantee high quality testing (other forms of testing can be neglected); the primary problem to be solved by test/DFT is defect detection (as opposed to defect isolation); parasitic effects can be ignored; test is a “stand-alone process”. Unfortunately, it is being discovered that deep submicron technologies invalidate many of these assumptions. It is suggested that increased emphasis should be placed on design and test generation techniques for delay defects. The industry should formalize an acceptable metric to measure the coverage of such defects. When and where appropriate, test generation software should comprehend parasitic effects and thereby create tests which are more robust with respect to test application. A tester model should be put into place to more easily debug test patterns without the necessity of actual silicon. Finally, test generation cannot be performed in a vacuum. There is a great deal of commonality between the design requirements for the use of static timing analysis and those of testability. There also must be a merging of functionalities, such as between critical path identification and path-based test generation, to ease the use of these technologies