By Topic

Scalable 128-bit AES-CM crypto-core reconfigurable implementation for secure communications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Armando Astarloa ; Department of Electronics and Telecommunications, University of the Basque Country, Spain ; Aitzol Zuloaga ; Jesus Lazaro ; Jaime Jimenez
more authors

A novel cryptographic core (cryptocore) approach for secure communications is presented in this work. It is an AES-Counter Mode core for System-on-Programmable-Devices that takes advantage from the flexibility of the reconfigurable devices. The proposed architecture is parameterizable, so it is easily scalable to fulfill different target area-speed trade-offs. This parametrization affects both the number of AES cipher block processors running in parallel and the implementation type. The crypto-core supports three AES cipher blocks implementations publicly available. The proposed architecture is analyzed with experimental results that show how the crypto-core eases and optimizes the secure communications implementation in different systems.

Published in:

Applied Electronics, 2009. AE 2009

Date of Conference:

9-10 Sept. 2009