Cart (Loading....) | Create Account
Close category search window

Effect of etch-clean delay time on post-etch residue removal for front-end-of-line applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Vos, Ingrid ; IMEC, Kapeldreef 75, 3001 Leuven, Belgium ; Hellin, David ; Vereecke, G. ; Pavel, Elizabeth
more authors

Your organization might have access to this article on the publisher's site. To check, click on this link: 

The benefits of integrating wet clean with plasma dry etch processes have been investigated. The studied applications included shallow trench isolation (STI), hardmask-based poly-silicon (poly-Si) gate, and nickel silicide (NiSi) contact etch. In particular, the novel technology Confined Chemical Cleaning has been evaluated using diluted hydrofluoric acid or an ammonia hydroxide–hydrogen peroxide mixture at short and controlled exposure times on the order of seconds. It was observed that the ability to remove post-etch residues using the same wet clean process diminished with increasing delay time between etch and clean, in the timescale of hours. In addition, a detrimental effect on the electrical performance was observed for the contact application. As shown, applying stronger cleaning conditions is one solution to remove residues (STI and poly-Si gate) or to restore the electrical performance (contact). However, the more aggressive residue removal process resulted in a higher substrate loss. The mechanism of the delay effect for the poly-Si gate application has been investigated. Evaluation of the post-etch residues using thermodesorption mass spectrometry revealed that post-etch residues were primarily inorganic in nature. Interaction of the post-etch residue and/or substrate with water vapor from the ambient environment is at the origin of the observed delay effects. The mechanism proposed is a hydrolysis of oxychlorine bound in the top layer of the residue, in combination with the dissolution of SiO2 residue material into silicic acid, resulting in a strengthening of the SiO2 network structure and hence increased resistance to wet cleaning. For the contact application, the electrical degradation of the contact resistance under “no clean” or “delayed clean” conditions was correlated w- ith the presence of an oxide layer at the metallic barrier/NiSi interface. This interfacial layer was not present for wafers with the integrated clean, which showed low contact resistances and high yield.

Published in:

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures  (Volume:27 ,  Issue: 5 )

Date of Publication:

Sep 2009

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.