Referenced Items are not available for this document.
The conventional DPLLs (digital phase-locked loops) are designed for Gaussian noise environment, and play important roles in carrier and clock recoveries. However, in power line communication (PLC), the power line noise is often impulsive, and then its statistical feature is different from Gaussian one. Therefore, we introduced Class A noise model in PLC first, and then proposed an optimum DPLL for such Class A noise environment using the techniques based on MAP (maximum A posteriori) estimating. The simulated results show the proposed DPLL has the smaller steady state phase errors than the conventional DPLL under Class A noise environment.
Published in:
Anti-counterfeiting, Security, and Identification in Communication, 2009. ASID 2009. 3rd International Conference on
Date of Conference: 20-22 Aug. 2009
- Page(s):
- 76 - 79
- E-ISBN :
- 978-1-4244-3884-6
- Print ISBN:
- 978-1-4244-3883-9
- INSPEC Accession Number:
- 10906151
- Conference Location :
- Hong Kong
- Digital Object Identifier :
- 10.1109/ICASID.2009.5276936
- Product Type:
- Conference Publications
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