By Topic

A Digital Phase-locked Loop based on MAP in PLC

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Zhilan Wu ; Inst. of Intell. Inf. Process., Guizhou Normal Univ., Guiyang, China

The conventional DPLLs (digital phase-locked loops) are designed for Gaussian noise environment, and play important roles in carrier and clock recoveries. However, in power line communication (PLC), the power line noise is often impulsive, and then its statistical feature is different from Gaussian one. Therefore, we introduced Class A noise model in PLC first, and then proposed an optimum DPLL for such Class A noise environment using the techniques based on MAP (maximum A posteriori) estimating. The simulated results show the proposed DPLL has the smaller steady state phase errors than the conventional DPLL under Class A noise environment.

Published in:

Anti-counterfeiting, Security, and Identification in Communication, 2009. ASID 2009. 3rd International Conference on

Date of Conference:

20-22 Aug. 2009