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Verification of a production cell using an automatic verification environment for VHDL

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2 Author(s)
R. Herrmann ; Corp. Res. & Dev., Siemens AG, Munich, Germany ; T. Reielts

This paper presents from the users point of view the automatic verification of nontrivial liveness properties for a reactive system implemented using VHDL. The aim is to make clear the simplicity, power and practical relevance of tools developed within the ESPRIT project FORMAT. For the specialist this paper provides a run through assumption commitment style verification and an overview of relevant publications

Published in:

Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European

Date of Conference:

18-22 Sep 1995