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A classification of design steps and their verification

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1 Author(s)
Ecker, W. ; Corp. Res. & Dev., Siemens AG, Munich, Germany

Hardware design using the hardware description language VHDL has to consider three independent property scales that influence the design process from an abstract level to the gate level, namely the design view, the timing aspect, and the value representation. Considering this classification, a systematic way for design steps and their verification with special emphasis on VHDL is presented in this paper

Published in:

Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European

Date of Conference:

18-22 Sep 1995

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