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A unified approach to the extraction of realistic multiple bridging and break faults

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2 Author(s)
Spiegel, G. ; Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany ; Stroele, A.P.

The presented fault model uniquely describes all structural changes in the transistor net list that can be caused by spot defects, including faults that connect more than two nets and faults that break a net into more than two parts. The developed analysis method extracts the complete set of realistic faults from the layout and for each fault computes the probability of occurrence

Published in:

Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European

Date of Conference:

18-22 Sep 1995