Referenced Items are not available for this document.
Design tools for ESD are described that ensure robust protection at both the cell and chip level in a high-volume, highly automated ASIC design system. There are three primary components: Design Rule Checking (DRC) for ESD; transient CDM simulations on extracted netlists; and analysis of chip-level power supply net resistances.
Published in:
Electrical Overstress/Electrostatic Discharge Symposium, 2004. EOS/ESD '04.
Date of Conference: 19-23 Sept. 2004
- Page(s):
- 1 - 8
- E-ISBN :
- 978-1-5853-7063-4
- Print ISBN:
- 978-1-5853-7063-4
- INSPEC Accession Number:
- 10915227
- Conference Location :
- Grapevine, TX
- Digital Object Identifier :
- 10.1109/EOSESD.2004.5272614
- Product Type:
- Conference Publications
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