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Parametric study of electroplating-based via-filling process for TSV applications

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5 Author(s)
K. Y. K. Tsui ; Hong Kong Applied Science & Technology Research Institute (ASTRI) 2 Science Park East Avenue, Hong Kong Science Park, Shatin, New Territories, Hong Kong, China ; S. K. Yau ; V. C. K. Leung ; P. Sun
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In this study, the effects of different influence factors on electroplating-based via-filling process were studied in a systematic manner. A through-silicon-via (TSV) chip was firstly designed, the chip size was 16 times 10 mm2 with the TSV interconnects. The via was in diameter of 50 mum and depth of 75 mum. The deep reactive ion etching (DRIE) technique was employed to fabricate the vias onto the silicon wafer. In order to fill up the vias by using the electroplating process, the SiO2 isolation layer was firstly prepared onto the sidewall and the defined surface of the wafer using the plasma enhanced chemical vapor deposition (PECVD) technique, the TiW barrier layer was prepared onto the SiO2 layer with the sputtering process, the Cu seed layer was then deposited onto the barrier layer by the sputtering process to provide a foundation for copper growth during electroplated deposition. To achieve the ldquobottom-uprdquo via-filling, the addictives were added into the copper plating solution. The results showed that the void free Cu filling can be achieved with an optimal additives ratio. The variation in both via opening and depth were found to be key factors influencing the via-filling quality. The process parameters such as current density, power waveform and so on were found to affect the vial filling quality. A comparison on the effects of key process parameters was made, showing that the current density, voltage waveform, and pulse reserve are three key parameters that affect the filling quality more than other parameters.

Published in:

Electronic Packaging Technology & High Density Packaging, 2009. ICEPT-HDP '09. International Conference on

Date of Conference:

10-13 Aug. 2009