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Fault location in Reed-Muller canonic networks

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1 Author(s)
Kodandapani, K.L. ; University of Regina, Department of Computer Science, Regina, Canada

In the paper, single and multiple-fault locating test sets for Reed-Muller canonic networks are derived. The fault model assumes stuck-at faults at the I/O leads of AND gates, and that an EOR gate under a fault can produce any other function of two inputs other than equivalence. The results in the paper give an insight into the complexity of testing of a class of logic networks.

Published in:

Electrical Engineers, Proceedings of the Institution of  (Volume:124 ,  Issue: 4 )

Date of Publication:

April 1977

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