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In this paper, a new technique is proposed for multiplication of two sampled analog signals and the output is in digital form. One analog signal is fed to the input of Delta sigma modulator (DSM1) after sampling. The sampled output of the second analog signal is negated or not negated depending on the bit state at the output of DSM1 and is fed to the input of second DSM (DSM2). The resulting bit stream at the output of DSM2 is the digital representation of the product of the two analog signals. For considered low frequency analog signals with amplitudes ranging from -2.5 V to +2.5 V, the maximum absolute value of error signal in the proposed multiplier is 0.05% of full scale (FS) when the sampling period of analog signals is 0.01 sec. and the DSMs operating clock period is 0.1 musec., whereas the reported accuracy so far is only 0.5%.