By Topic

Analog Multiplier with High Accuracy

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Diwakar, K. ; Fac. of Eng. & Technol., Multimedia Univ., Ayer Keroh, Malaysia ; Senthilpari, C. ; Singh, A.K. ; Lim Way Soong

In this paper, a new technique is proposed for multiplication of two sampled analog signals and the output is in digital form. One analog signal is fed to the input of Delta sigma modulator (DSM1) after sampling. The sampled output of the second analog signal is negated or not negated depending on the bit state at the output of DSM1 and is fed to the input of second DSM (DSM2). The resulting bit stream at the output of DSM2 is the digital representation of the product of the two analog signals. For considered low frequency analog signals with amplitudes ranging from -2.5 V to +2.5 V, the maximum absolute value of error signal in the proposed multiplier is 0.05% of full scale (FS) when the sampling period of analog signals is 0.01 sec. and the DSMs operating clock period is 0.1 musec., whereas the reported accuracy so far is only 0.5%.

Published in:

Computational Intelligence, Communication Systems and Networks, 2009. CICSYN '09. First International Conference on

Date of Conference:

23-25 July 2009