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Analysis of bus hierarchies for multiprocessors

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2 Author(s)
D. C. Winsor ; Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA ; T. N. Mudge

To build large shared-memory multiprocessor systems that take advantage of current hardware-enforced cache coherence protocols, an interconnection network is needed that acts logically as a single bus while avoiding the electrical loading problems of a large bus. Models of bus delay and bus throughput are developed to aid in optimizing the design of such a network. These models are used to derive a method for determining the maximum number of processors that can be supported by each of several bus organizations, including conventional single-level buses, two-level bus hierarchies, and binary tree interconnections. An example based on a TTL bus is presented to illustrate the methods and to show that shared-memory multiprocessors with several dozen processors are feasible using a simple two-level bus hierarchy

Published in:

Computer Architecture, 1988. Conference Proceedings. 15th Annual International Symposium on

Date of Conference:

30 May-2 Jun 1988