By Topic

A simulation study of two-level caches

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Short, R.T. ; DECwest Eng., Bellevue, WA, USA ; Levy, H.M.

A trace-driven simulation study to examine the effect of a two-level cache hierarchy in uniprocessors is reported. A simulation model of a multiple-cycle-per-instruction processor was constructed to estimate the total cycles required to execute a synthetic benchmark. Results show that a second-level cache can be used to increase system performance when main memory access times are large relative to CPU cycle time. For example, the addition of a four-cycle 64 K second-level cache following a one-cycle, 8 K first-level cache increases performance by 15% when used in a system with a 15-cycle primary memory. Second-level caches are shown to be particularly effective when used behind small on-chip caches; adding an 8 K second-level to a 1 K first-level increases performance by 26%, assuming similar parameters. The performance impact of different write strategies and separate instruction and data caches are also evaluated

Published in:

Computer Architecture, 1988. Conference Proceedings. 15th Annual International Symposium on

Date of Conference:

30 May-2 Jun 1988