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A 16 bit low-power-consumption digital signal processor using a 80 MOPS redundant binary MAC

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11 Author(s)
Kabuo, H. ; Semicond Res. Centre, Matsushita Electr. Ind. Co. Ltd., Kadoma, Japan ; Okamoto, M. ; Tanaka, R. ; Yasoshima, H.
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This paper describes a 16b fixed point digital signal processor (DSP), especially a variable pipeline multiply-accumulate (MAC) unit using a redundant binary representation. This new MAC unit improves 9.8% in power consumption and 249b in operation speed at multiply and multiply-accumulate operation over a conventional MAC unit. This chip is fabricated with a 0.5 um double-metal-layer CMOS process and achieves 40 MIPS and 80 MOPS-peak performance.

Published in:

VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on

Date of Conference:

8-10 June 1995

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