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A low-power single-chip microprocessor with multiple page-size MMU for nomadic computing

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15 Author(s)
Narita, S. ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; Ishibashi, K. ; Tachibana, S. ; Norisue, K.
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A low-power single-chip RISC microprocessor has been designed. It based on Hitachi's SH architecture with multiple page-size MMU. An automatic-power-save cache memory reduces the power dissipation at low frequencies, Two low-power modes and a module-stop function are software programmable for system power management. MMU supports 4 KB and 1 KB page-sizes by 4-way set-associative TLB. The chip using 0.5 um CMOS technology is fabricated, and achieves 60 Dhrystone MIPS and keeps 600 mW (max.), 60 MHz at worst condition.

Published in:

VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on

Date of Conference:

8-10 June 1995

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