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Power-efficient metastability error reduction in CMOS flash A/D converters

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2 Author(s)
C. L. Portmann ; Center for Integrated Syst., Stanford Univ., CA, USA ; T. H. Y. Meng

This paper introduces a CMOS flash A/D architecture with an external pipelining scheme to reduce metastability errors with minimal power and area overhead. Unresolved comparator outputs due to metastability are held high to maintain one valid word line in the encode ROM. A Gray code is used in the ROM to pass errors as a single unsettled bit to the converter output. Errors can then be reduced with only n latches per pipeline stage instead of 2/sup n/, reducing area and power overhead with comparable error rates to internal pipelining schemes.

Published in:

VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on

Date of Conference:

8-10 June 1995