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Low power Gb/s CMOS interfaces

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2 Author(s)
Ohtomo, Y. ; NTT LSI Labs., Kanagawa, Japan ; Nogawa, M.

For high-speed digital systems, it is important to develop point-to-point Gb/s interfaces that consume low power during low-transition-rate operation. This paper presents two novel Gb/s CMOS interfaces. One uses an active-pull-up (APU) technique to raise the maximum transmission speed. In the other interface, the transmission wave form is changed from digital to impulse to markedly reduce power consumption at low transition rate.

Published in:

VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on

Date of Conference:

8-10 June 1995