Referenced Items are not available for this document.
We propose a high speed and low power data transfer scheme for the wide internal data bus of an AS-Memory using the asynchronous compressed pulse width modulation (AC-PWM) technique and an automatic gain controlled (AGC) amplifier. The maximum bit rate per bus of AC-PWM increases by 12 times that of the conventional 100MHz data bus. The AGC amplifier achieves a fast data output while reducing by 1/3 the standby current. The proposed architecture is a key advance in the future development of AS-Memories.
Published in:
VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on
Date of Conference: 8-10 June 1995
- Page(s):
- 27 - 28
- Meeting Date :
- 08 Jun 1995-10 Jun 1995
- Print ISBN:
- 0-7800-2599-0
- INSPEC Accession Number:
- 5212052
- Conference Location :
- Kyoto, Japan
- Digital Object Identifier :
- 10.1109/VLSIC.1995.520672
- Product Type:
- Conference Publications
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