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A 500 MHz 1-stage 32 bit ALU with self-running test circuit

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6 Author(s)
Yoshida, T. ; ULSI Res. Center, Toshiba Corp., Kawasaki, Japan ; Matsubara, G. ; Yoshioka, S. ; Tago, H.
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A 500 MHz 1-stage 32 bit ALU has been designed and fabricated using 0.3 /spl mu/m CMOS process. Main features are a 1.56 ns DPL (Double path-transistor logic) adder and a compact barrel shifter using a newly developed 4-input MUX scheme. A BIST (built-in self test) circuit enables 500 MHz real-time testing. The chip size is 1 mm/spl times/0.38 mm.

Published in:

VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on

Date of Conference:

8-10 June 1995

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