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A 0.4 /spl mu/m 1.4 ns 32b dynamic adder using non-precharge multiplexers and reduced precharge voltage technique

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4 Author(s)
A. Inoue ; Fujitsu Labs. Ltd., Kanagawa, Japan ; Y. Kawabe ; Y. Asada ; S. Ando

This paper describes fast 32-bit dynamic adder using nonprecharge multiplexers and reduced precharge voltage technique. Design adopting novel multiplexers reduces transistor count, resulting in the reduction of total parasitic capacitance. Reduced precharge voltage makes the discharge time shorter. Experimental circuit has been fabricated using 0.4 /spl mu/m CMOS technology and we confirmed the delay of 1.4 ns at the supply voltage of 3.3 V at room temperature.

Published in:

VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on

Date of Conference:

8-10 June 1995