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Next generation I/O power delivery design through SIPD co-analysis & comprehensive platform validation

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2 Author(s)
Yee Hung See Tau ; Intel Microeelctronics(M) Sdn Bhd, Penang Design Center (PDC), Bayan Lepas FTZ Phase 3, 11900, Malaysia ; Marcus Chan

This paper illustrates many different approaches in solving I/O power delivery noise issues and walk through pre-silicon design solution. It covers circuit and architectural design influence, on silicon and on board decoupling solutions selection and package and platform design optimization. SIPD co-simulations and appropriate package return path are the main topic to discuss in this paper and certainly impedance (Z) profile and transient analysis will be performed to observe the noise frequency and accurately address the root cause. All the above will be verified through comprehensive validation data.

Published in:

Quality Electronic Design, 2009. ASQED 2009. 1st Asia Symposium on

Date of Conference:

15-16 July 2009