Scheduled System Maintenance:
On May 6th, single article purchases and IEEE account management will be unavailable from 8:00 AM - 12:00 PM ET (12:00 - 16:00 UTC). We apologize for the inconvenience.
By Topic

The impact of timing yield improvement under process variation on flip-flops soft error rate

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Mostafa, H. ; Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada ; Anis, M. ; Elmasry, M.

In deeply pipelined synchronous systems, any violation of the timing constraints of the flip-flops can cause the overall system to malfunction. Due to CMOS technology scaling, increased process variations result in a large delay variability causing unacceptable loss in the timing yield. Several variation tolerant techniques are introduced to mitigate this variability challenge by improving the timing yield. In the mean time, devices are getting smaller, faster, and operating at lower supply voltages. These reduced capacitances and power supply voltages combined with the increased chip density to perform more functionality increase the soft errors susceptibility and make it one of the essential design challenges. Moreover, there are many flip-flops topologies that vary in their relative performance and power consumption which make the selection decision very difficult to flip-flops designers especially under variability and soft errors challenges. Therefore, a comparative analysis between these different flip-flops topologies considering these scaling challenges is beneficial to guide the flip-flops designers in selecting the best topology for their specific application constraints. This paper presents a comparative analysis of the timing yield improvement impact on flip-flops soft error rate by using the STMicroelectronics 65-nm CMOS technology. The analyzed flip-flops are compared for power and power-delay product (PDP) overheads to achieve this timing yield improvement. Then, they are compared for the soft error susceptibility. Finally, it is shown that the timing yield improvement improves the flip-flops soft error immunity significantly.

Published in:

Quality Electronic Design, 2009. ASQED 2009. 1st Asia Symposium on

Date of Conference:

15-16 July 2009