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Phase noise is one of the most restricted specifications in oscillators, especially ring oscillators. Phase noise will exhibit large fluctuations around its nominal value due to the increased process variation with technology scaling. These fluctuations will cause some fabricated ring oscillators not to meet the phase noise constraint and, hence, result in yield loss. This yield loss is expected to become worse especially for sub-90-nm technology nodes. In this paper, an analytical model for the phase noise variability in ring oscillators is proposed. The proposed model has been verified using Monte Carlo SPICE simulations for an industrial 65-nm CMOS technology and is found in good agreement. The model shows that for the commonly used differential-pair-based ring oscillators, the main contribution in phase noise variability comes from the differential pair tail transistor. It also shows that the phase noise variability is reduced as the supply voltage increases. These results can be used to mitigate the phase noise variability and improve the yield through proper sizing of the tail transistor or higher supply voltage.