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A CMOS frequency generation system for W-band radars, including a phase-locked loop (PLL) (55–60 GHz) with a frequency-divided-by-2 output and an offset mixer for generation of a W-band carrier (83–90 GHz) is realized using low leakage transistors of a low cost 65-nm bulk CMOS process. The phase noise of PLL is as low as −87 and −112 dBc/Hz at 1 and 10 MHz offsets. The PLL consumes 46 mW. The total frequency generation system consumes ∼180 mW.
VLSI Circuits, 2009 Symposium on
Date of Conference: 16-18 June 2009