Scheduled System Maintenance:
On Wednesday, July 29th, IEEE Xplore will undergo scheduled maintenance from 7:00-9:00 AM ET (11:00-13:00 UTC). During this time there may be intermittent impact on performance. We apologize for any inconvenience.
By Topic

Application modelling and hardware description for network-on-chip benchmarking

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Salminen, E. ; Tampere Univ. of Technol., Tampere, Finland ; Grecu, C. ; Hamalainen, T.D. ; Ivanov, A.

Measuring and comparing performance, cost and other features of advanced communication architectures for complex multicore/multiprocessor systems on chip is a significant challenge which has hardly been addressed so far. This article presents a modelling concept for applications running on multicore systems and defines an extensible markup language (XML) format for documenting and distributing network-on-chip (NoC) benchmarks. It defines a black-box view of the processing elements that discloses only the computational aspects that are relevant in interacting with the on chip data transport mechanism. The purpose is to lay the groundwork for a standardised NoC benchmark set.

Published in:

Computers & Digital Techniques, IET  (Volume:3 ,  Issue: 5 )