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Memory-centric network-on-chip for power efficient execution of task-level pipeline on a multi-core processor

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5 Author(s)
Kim, D. ; Div. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea ; Kim, K. ; Kim, J.-Y. ; Lee, S.
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For flexible mapping of various task-level pipelines on a multi-core processor, the authors proposed the memory-centric network-on-chip (NoC). The memory-centric NoC manages producer-consumer data transactions between the tasks in the case of task-level pipelines are distributed over multiple processing cores. Since the memory-centric NoC manages the data transactions, it relieves burden of the software running on the processing cores and this results in power-efficient execution of task-level pipeline. To prove advantages of the memory-centric NoC, the authors implemented a multi-core processor based on the memory-centric NoC.

Published in:

Computers & Digital Techniques, IET  (Volume:3 ,  Issue: 5 )