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A Power-Scalable Switch-Based Multi-processor FFT

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2 Author(s)
Bassam Jamil Mohd ; Qualcomm, Inc., San Diego, CA, USA ; Earl E. Swartzlander Jr.

This paper examines the architecture, algorithm and implementation of a switch-based multi-processor realization of the fast Fourier transform (FFT). The architecture employs M processing elements (PEs), and provides a speedup of M compared with systems that use a single PE. An algorithm is provided to detect and resolve memory conflicts. A CMOS implementation of a four-PE processor is presented. The design is reconfigurable to compute various FFT sizes. The design power consumption is scalable based on the number of active PEs. The timing, area and power results are discussed.

Published in:

2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors

Date of Conference:

7-9 July 2009