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An FPGA-based Parallel Hardware Architecture for Real-Time Face Detection Using a Face Certainty Map

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6 Author(s)
Seunghun Jin ; Dept. of Electr. & Comput. Eng., Sungkyunkwan Univ., Suwon, South Korea ; Dongkyun Kim ; Thuy Tuong Nguyen ; Bongjin Jun
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This paper presents an FPGA-based parallel hardware architecture for real-time face detection. An image pyramid with twenty depth levels is generated using the input image. For these scaled-down images, a local binary pattern transform and feature evaluation are performed in parallel by using the proposed block RAM-based window processing architecture. By sharing the feature look-up tables between two corresponding scaled-down images, we can reduce the use of routing resources by half. For prototyping and evaluation purposes, the hardware architecture was integrated into a Virtex-5 FPGA. The experimental result shows around 300 frames per second speed performance for processing standard VGA (640times480times8) images. In addition, the throughput of the implementation can be adjusted in proportion to the frame rate of the camera, by synchronizing each individual module with the pixel sampling clock.

Published in:

Application-specific Systems, Architectures and Processors, 2009. ASAP 2009. 20th IEEE International Conference on

Date of Conference:

7-9 July 2009

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