Cart (Loading....) | Create Account
Close category search window
 

Test generation for linear analog circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Weiwei Mao ; Ford Microelectron. Inc., Colorado Springs, CO ; Yunsheng Lu ; Gulati, R.K. ; Dandapani, R.

A test generation method for linear analog circuits is presented. The method is based on frequency domain analysis. The faults considered are abnormal value changes of elements, e.g., resistors, capacitors and inductors. The effect of design tolerance is considered in test generation. A procedure to determine the output ranges for acceptance or rejection is also proposed. The proposed method has been applied to several circuits at board level to generate test conditions for all elements to be tested. The method is also able to indicate which elements in the circuit are hard to test

Published in:

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Date of Conference:

1-4 May 1995

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.