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A two million gate 0.35 μm CMOS ASIC family

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1 Author(s)
C. M. Smith ; NEC Electron. Inc., Mountain View, CA, USA

A two million gate gate array has been developed using a 0.35 μm CMOS sea-of-gates technology. In addition to the large integration capacity of the gate array, it also supports high speed I/O interface standards at voltages from 5 V to 1.4 V with a unique I/O power ring structure. Phase-locked loops (PLL) and clock skew management enable the technology to deliver speeds of up to 156 MHz at 3.3 V

Published in:

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Date of Conference:

1-4 May 1995