A two million gate 0.35 /spl mu/m CMOS ASIC family

A two million gate gate array has been developed using a 0.35 /spl mu/m CMOS sea-of-gates technology. In addition to the large integration capacity of the gate array, it also supports high speed I/O interface standards at voltages from 5 V to 1.4 V with a unique I/O power ring structure. Phase-locked loops (PLL) and clock skew management enable the technology to deliver speeds of up to 156 MHz at 3.3 V.