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A supply-regulated phase-locked loop (PLL) employs a split-tuned architecture to decouple the tradeoff between supply-noise rejection performance and power consumption. By placing the regulator in the low-bandwidth coarse loop, the proposed PLL architecture allows us to maximize its bandwidth to suppress the oscillator phase noise with neither the power supply-noise rejection nor the power dissipation of the regulator being affected. A replica-based regulator introduces a low-frequency pole in its supply-noise transfer function and avoids degradation of supply-noise rejection beyond the regulator-loop's dominant pole frequency. The prototype PLL fabricated in a 0.18 mum digital CMOS process operates from 0.5 to 2.5 GHz. At 1.5 GHz, the proposed PLL achieves 1.9 ps long-term rms jitter and a worst case supply-noise sensitivity of -28 dB (0.5 rad/V), an improvement of 20 dB over conventional solutions, while consuming 2.2 mA from a 1.8 V supply.