By Topic

Novel hybrid CMOS and CNFET inverting amplifier design for area, power and performance optimization

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Fahad Ali Usmani ; Department of Electronics Engineering, Aligarh Muslim University, India ; Mohd. Hasan

There is a pressing need to explore circuit design ideas in new emerging technologies in deep-submicron in order to exploit their full potential during the early stages of their development. Carbon nanotube based technology (CNT) has significant potential to replace silicon technology sometimes in the future. This paper presents an optimal design of hybrid CMOS and carbon nanotube field effect transistor (CNFET) based complementary type inverting amplifier for area-power-performance optimization in terms of operating voltage, number of nanotubes, diameter and pitch of the CNFET along with the qualitative explanation of the obtained results at an operating voltage of 0.9 V using HSPICE simulations. Furthermore, comparison of hybrid technology amplifiers with planar CMOS at the 32 nm technology node showed that the performance of PMOS-NCNFET configuration is better in terms of Gain (62% higher), GBP (fT, 181% higher), slew rate (163% higher) etc. while PCNFET-NMOS outperforms in terms of Gain (59% higher), Bandwidth (332% higher), GBP (395%), Output resistance (328% lower) for typical load capacitance (CL = 1fF) at the cost of higher power consumption.

Published in:

Electron Devices and Semiconductor Technology, 2009. IEDST '09. 2nd International Workshop on

Date of Conference:

1-2 June 2009