Referenced Items are not available for this document.
Data retention time for ultimate DRAMs with an extremely scaled-down cell size has been investigated. The entire memory cells can be discretely categorized by two groups: leaky cells or normal cells, and the main distribution representing the normal cells shows longer than 40 s of the mean retention time. The leaky cells are mainly originated by trap-assisted gate-induced drain leakage currents depending on trap energy dispersion. Through analyses of full chip retention failure curves and interface trap density ( Dit*) measurements, we propose that the tail distribution will be diminished and separated from the main distribution as the cell size shrinks into a true nanoscale. As a result, the retention time is eventually to be determined by the main distribution function only.
Published in:
Electron Device Letters, IEEE
(Volume:30
,
Issue:
8
)
Date of Publication: Aug. 2009
- Page(s):
- 846 - 848
- ISSN :
- 0741-3106
- INSPEC Accession Number:
- 10793181
- Digital Object Identifier :
- 10.1109/LED.2009.2023248
- Product Type:
- Journals & Magazines
- Date of Publication :
- 14 July 2009
- Date of Current Version :
- 24 July 2009
- Issue Date :
- Aug. 2009
- Sponsored by :
- IEEE Electron Devices Society
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