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The Role of PLLs in Future Wireline Transmitters

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1 Author(s)
Behzad Razavi ; Dept. of Electr. Eng., Univ. of California, Los Angeles, CA, USA

As data rates in wireline transmitters approach 80-100 Gb/s, phase-locked loops emerge as a serious bottleneck, requiring co-design of the clock and data paths. This paper describes speed, skew, and jitter issues at these rates and formulates the corruption due to effects such as the reference phase noise and the loop filter leakage. The phase noise performance of cascaded loops is also analyzed and a new transmitter architecture is proposed that substantially relaxes the speed and skew requirements.

Published in:

IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:56 ,  Issue: 8 )