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Technology mapping algorithms for sequential circuits using look-up table based FPGAS

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2 Author(s)
Habib, S. ; Dept. of Comput. Sci., Graduate Sch. of City Univ. of New York, NY, USA ; Quan Xu

This paper presents a set of algorithms for mapping sequential circuits onto look-up table based FPGAs and explores how it is possible to reduce the time delay and simplify the final routing results of this mapping. We define several new terms which are used to describe the problem. This work focuses on the mapping of flip-flops and their adjacent combinational parts in sequential circuits using LUT based FPGAs

Published in:

VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on

Date of Conference:

16-18 Mar 1995