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Design and analysis of a low-power energy-recovery adder

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2 Author(s)
Tzartzanis, N. ; Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA, USA ; Athas, W.C.

In this paper, an 8-bit energy-recovery adder design is evaluated through SPICE simulation for energy dissipation and delay time, and is compared against a supply-voltage-scaled adder. The experimental results indicate that the energy-recovery adder outperforms the supply-scaled version for a wide range of frequencies

Published in:

VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on

Date of Conference:

16-18 Mar 1995