Skip to Main Content
Yield loss caused by random defects is an important manufacturability concern. Random yield of modern integrated circuits is associated with layout sensitivity to defects defined as the ratio of critical area to the overall layout area. This paper proposes a methodology to predict random yield with high fidelity based on a stochastic layout sensitivity model that uses very basic layout information. The model has very important applications including pre-layout yield prediction and yield forecasting for future process technologies.
Date of Publication: Aug. 2009