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Optimizing a 32nm development fab's HOL defect pareto using iDO and eADC

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3 Author(s)
C. A. Boye ; IBM Corporation, 257 Fuller Road Albany, NY 12203, USA ; N. Yathapu ; S. Kini

This paper presents a methodology for optimizing a fab defect pareto for 32 nm Health of Line (HOL). HOL involves running a selected product as a means of generating defect baseline paretos and electrical test for key process sectors. Optimizing HOL pareto consists of increasing the capture of key yield limiting defects and minimizing the capture of non yield limiting defects. This was achieved by implementing smart binning (iDO) on the BF inspection system in conjunction with auto defect classification (eADC) on the SEM review tool.

Published in:

2009 IEEE/SEMI Advanced Semiconductor Manufacturing Conference

Date of Conference:

10-12 May 2009