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Minimum power fail in high density structure improved by Chemical and Mechanical Polishing optimization

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11 Author(s)
L. Denis ; Altis Semiconductor, 224 Bd JF Kennedy, 91105 Corbeil Essonnes, FRANCE ; V. Dureuil ; C. Fournier ; G. Richou
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A yield loss previously never seen occurred on a 0.13 mum technology node product for RF applications. Unfortunately, the in-line monitoring was not successful to catch the problem. Defective chips have been analysed to identify the rootcause mechanism. Failure Analysis and RX layout inspection on the leaky parts pointed out a structure within the chip with a specific design characterized by a high Active Area/Oxide ratio compared to SRAM: the Power Management Unit (PMU) macro. Construction analysis and SEM cross sections identified the problem in Shallow Trench Isolation (STI) module and revealed a too high step height in the PMU macro inducing poly-silicon shorts. To fix the problem, different process improvements have been implemented in STI Chemical and Mechanical Polishing (CMP). The first action addressed the global planarization by a higher polish time and a higher carrier speed. The second improvement affected the local planarization thanks to a dresser change.

Published in:

2009 IEEE/SEMI Advanced Semiconductor Manufacturing Conference

Date of Conference:

10-12 May 2009