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For mature technologies, main yield detractor is random defectivity. Nevertheless, some devices present higher defectivity than rest of devices. Out of process accident, design related defect is one of suspected root cause. Also, design-based defect type is expected to increase as technology node decreases. Determining origin of these additional systematic defects is not easy as these defects are usually residual for technologies in production, not always predictable by OPC simulator (ex: void defect in active STI structure), and at least hidden by random defectivity after classical wafer inspection control. In this paper, an automatic flow to track systematic defects within global defectivity is presented. This flow starts with a relevant selection of several inspection defect files for a given layer. Then the Design Based Binning (DBB) tool performs a fine alignment of the whole multi inspection defect data set with design file. The resulting aligned defect file is treated by an efficient pattern matching algorithm to generate a design-based binning (DBB) defect file. The integration of this output defect file into a defect database allows easy defect analysis and statistical correlation to electrical results. An example of a suspected design-based defect analysis for a 90 nm node device is presented at the end of this paper.