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Micronets: a model for decentralising control in asynchronous processor architectures

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3 Author(s)
Arvind, D.K. ; Dept. of Comput. Sci., Edinburgh Univ., UK ; Mullins, R.D. ; Rebello, V.

Micronets model processor architectures as a network of communicating resources, in contrast to the traditional one of a linear pipeline. Micronets distribute the control to the functional units, which enables the exploitation of fine-grain concurrency between instructions. The overhead due to asynchrony is hidden with the four-phase protocol being used to implement scoreboarding and hazard avoidance mechanisms, without incurring additional control costs. This paper demonstrates the feasibility of micronet-based processors. Results are presented for SPICE-level simulations of a 0.7 μm CMOS implementation of a datapath. The relationships between micronets and both the compiler and the computer architecture are also explored

Published in:

Asynchronous Design Methodologies, 1995. Proceedings., Second Working Conference on

Date of Conference:

30-31 May 1995

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