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Technology mapping of timed circuits

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3 Author(s)
C. J. Myers ; Comput. Syst. Lab., Stanford Univ., CA, USA ; P. A. Beerel ; T. H. -Y. Meng

This paper presents an automated procedure for the technology mapping of timed circuits to practical gate libraries. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification which is used throughout the design process to optimize the implementation. Our procedure begins with a timed specification and a delay-annotated gate library description which must include 2-input AND gates, OR gates, and C-elements, but optionally can include higher-fanin gates, AND-OR-INVERT blocks, and generalized C-elements. Our procedure first generates a technology-independent timed circuit netlist composed of possibly high-fanin AND gates, OR gates, and 2-input C-elements. The procedure then investigates simultaneous decompositions of all high-fanin gates by adding state variables to the the specification and performing resynthesis. Although multiple decompositions are explored timing information is utilized to significantly reduce their number. Once all gates are sufficiently decomposed, the netlist can be mapped to the given gate library, taking advantage of any compact complex gates available. The decomposition and resynthesis steps have been fully automated within the synthesis tool ATACS and we present results for several examples

Published in:

Asynchronous Design Methodologies, 1995. Proceedings., Second Working Conference on

Date of Conference:

30-31 May 1995