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High-level test evaluation of asynchronous circuits

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1 Author(s)
van de Wiel, R. ; Dept. of Math. & Comput. Sci., Eindhoven Univ. of Technol.

The present a method for evaluating production fault tests for asynchronous circuits. A novel fault model is defined, based on a high-level circuit description, allowing the evaluation of production tests on the design level. This evaluation method is used in the test generation for an asynchronous 22 k transistor DCC error corrector IC, resulting in a fault coverage of 99.8%

Published in:

Asynchronous Design Methodologies, 1995. Proceedings., Second Working Conference on

Date of Conference:

30-31 May 1995