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A very fast three-mode retiming PLL with low jitter and wide operating margin

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3 Author(s)
H. Shirahama ; Kyushu Univ., Fukuoka, Japan ; K. Taniguchi ; O. Tsukahara

The proposed PLL realizes a fast and wide-ranging pull-in, and a stable locked condition by controlling a frequency difference detector and a PLL core with a dual loop constants in three modes. Simulations of the PLL designed with an 0.8 μm bipolar devices and experiments using a PLL-IC together with PLAs demonstrated the features; a short pull-in time comparable to SAW filters even for 63 bit PRBS NRZ inputs, low output jitter and no slowly-recovering phase error

Published in:

Circuits and Systems, 1994. APCCAS '94., 1994 IEEE Asia-Pacific Conference on

Date of Conference:

5-8 Dec 1994