By Topic

Design of reconfigurable logic controllers from hierarchical UML state machines

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Adamski, M. ; Inst. of Comput. Eng. & Electron., Univ. of Zielona Gora, Zielona Gora

The paper presents a formal design methodology for reconfigurable, modular digital controller logic synthesis. The project of embedded controller starts from behavioral, graphical hierarchical and concurrent state machine description in Unified Modeling Language (UML). After the hierarchical encoding of nested and concurrent superstates, the UML state machine diagram can be directly and automatically mapped into the structured array of cells in Field Programmable Gate Array (FPGA). The design process goes through rule-based symbolic assertions on the behavioral level to propositional logic expressions in Register Transfer Level, which are automatically rewritten in Hardware Description Languages (VHDL or Verilog). The transformation from specification to implementation is partially supported by a computer theorem prover changing the symbolic form of complex UML state machine specification given in the Gentzen sequent logic into simple textual rule-based statements. They are directly accepted by commercial HDL tools for simulation and effective logic synthesis.

Published in:

Industrial Electronics and Applications, 2009. ICIEA 2009. 4th IEEE Conference on

Date of Conference:

25-27 May 2009