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PLA based synthesis and testing of hazard free logic

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4 Author(s)
Bhattacharyya, U.K. ; Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India ; Gupta, I.S. ; Shyama Nath, S. ; Dutta, P.

This paper presents a divide and conquer approach for the hazard-free realization of combinational networks. The circuit is partitioned into a set of supergates which are individually made hazard-free. Since each supergate has to be implemented in two-level form, the circuit can be implemented as a multilevel network of PLAs. A modified supergate partitioning for multi-output circuits has also been proposed. Experiments to evaluate the testability of the synthesized circuits have been carried out

Published in:

VLSI Design, 1995., Proceedings of the 8th International Conference on

Date of Conference:

4-7 Jan 1995